1. Field of the Invention
The present invention relates to a pulse output circuit which converts, for example, an input pulse signal to a predetermined level and supplies it to a circuit having a high capacitive load.
2. Description of the Related Art
For example, normally an amplifying circuit such as a video signal amplifying circuit in a computer display monitor handles a pulse signal including signal components of a wide bandwidth up to several hundreds of mega-hertz (MHz).
In the above amplifying circuit, it is sometimes necessary to buffer a pulse signal input to the amplifying circuit with a high through-rate so as to drive a circuit having a high capacitive load. For example, in the case of a video signal of a computer display monitor, the video signal cannot be faithfully reproduced on the computer display monitor if the pulse signal cannot be output at a high through-rate.
Here, as shown in FIG. 9, consider a circuit having a gain control amplifying circuit 50 which buffers a pulse signal and outputs it to a circuit having a high capacitive load C.sub.0 provided at the following stage.
An input pulse signal S.sub.IN is input to a gain control circuit 51 in which the gain is automatically controlled and then is output to an output buffer circuit 52 as a pulse signal of a constant level.
The output buffer circuit 52 converts the input pulse signal having a predetermined level and outputs a pulse signal S.sub.OUT to a circuit having a high capacitive load C.sub.0 provided at the following stage.
FIGS. 1 and 2 are views of specific examples of the output buffer 52.
The output buffer circuit shown in FIG. 1 is connected to a circuit having a high capacitive load C.sub.0 at the output stage and is comprised of npn-type transistors Q51 to Q54 and a resistor R51.
In FIG. 1, an emitter of the transistor Q51 and a collector of the transistor Q52 are connected and a collector of the transistor Q51 is connected to a supply line of a power source voltage vcc.
A base of the transistor Q51 is connected to an input terminal T.sub.IN.
Bases of transistors Q52 and Q54 are mutually connected and a direct current (DC) voltage is applied to them.
An emitter of the transistor Q52 is connected to a ground line GND.
A collector of the transistor Q53 is connected to the supply line of the power source voltage VCC, and an emitter of the transistor Q53 is connected to a collector of the transistor Q54.
One end of the resistor R51 is connected to the base of the transistor Q53 and the other end thereof is connected to the connection line of the emitter of the transistor Q51 and the collector of the transistor Q52.
The collector of the transistor Q53 is connected to the supply line of the power source voltage VCC.
The connection line of the emitter of the transistor Q53 and the collector of the transistor Q54 is connected to the output terminal T.sub.OUT.
One end of the capacitive load C.sub.0 is connected to the output terminal T.sub.OUT and the other end thereof is connected to the ground line GND.
In the circuit shown in FIG. 1, the transistors Q51 and Q53 are formed as emitter-follower circuits and the transistors Q53 and Q54 have sufficiently larger current driving abilities compared with other transistors Q51 and Q52. A bias voltage is applied to the bases of the transistors Q52 and Q54, and the transistors Q52 and Q54 are in a conductive state.
In the circuit shown in FIG. 1, when a pulse signal S.sub.IN having the waveform shown in FIG. 6 is input to the input terminal T.sub.IN, a current i.sub.0 flows to the register R51, a base bias current flows to the base of the transistor Q53, and an emitter current i.sub.1 at the transistor Q53 increases.
Since the current driving ability of the transistor Q54 is smaller than that of the transistor Q53, a part of the emitter current i.sub.1 flows into the transistor Q54 and the remaining current flows into the capacitive load C.sub.0, therefore, the capacitive load C.sub.0 is charged.
The output voltage at the output terminal T.sub.OUT changes as shown in the portion (1) in FIG. 6.
At a trailing edge of the pulse signal S.sub.IN, the supply of the emitter current at the transistor Q1 sharply falls so that the capacitive load C.sub.0 is no longer charged. The charge in the capacitive load C.sub.0 is discharged to the ground line GND through the transistor Q54. At this time, the output terminal T.sub.OUT and the output voltage S.sub.OUT change as shown in the portion (2) in FIG. 6.
Accordingly, when the amount of the collector current of the transistor Q54 is small and the capacitance of the capacitive load C.sub.0 is large, there is a disadvantage that the through-rate during the fall of the pulse signal S.sub.IN deteriorates further.
Also, since current is always flowing from the emitter of the transistor Q54, there is a disadvantage that the power consumption becomes relatively high.
FIG. 2 shows a circuit comprised of the circuit shown in FIG. 1 where the transistor Q54 is replaced by the resistor R52.
In the case of the circuit shown in FIG. 2, the time required for discharging the capacitive load C.sub.0 at the trailing edge of the pulse signal S.sub.IN is determined by a time constant determined by the capacitive load C.sub.0 and the resistor R52.
Accordingly, by setting the time constant determined by the capacitive load C.sub.0 and the resistor R52 short, the through-rate at the trailing edge of the pulse signal S.sub.IN improves.
However, the power consumption by the resistor R52 and the transistor Q53 becomes large, which is not preferable in configuring a circuit.